FIG. 1 diagrammatically illustrates a conventional arrangement including a binary ripple counter 12 coupled to a sampler 11 that samples the output bits D0, D1, D2, etc. from respective count stages of the binary ripple counter. Such an arrangement is useful in many applications. One example is determining the phase of a digitally controlled oscillator (DCO). The structure and operation of the binary ripple counter 12 and the sampler 11 shown in FIG. 1 are known in the art. (See, e.g., US Patent Publication No. 2005/0195917, and U.S. Ser. No. 12/134,081 entitled “A Low Power All Digital PLL Architecture”, filed Jun. 5, 2008, both of which are incorporated herein by reference.) A series configuration of delay elements 13, 14, etc. functions as a sampling controller that produces respectively delayed versions, C1, C2, etc., of a base sample clock signal CO, which is in turn a delayed version of an input clock signal denoted as Clock 2. The clock signals C0, C1, C2, etc. are sample control signals used to clock respective latch stages of sampler 11 that sample the respective output bits D0, D1, D2, etc. A count clock signal, denoted as Clock 1, drives the binary ripple counter 12.
The sampling operations performed by the arrangement of FIG. 1 can be challenging at high operating speeds, due to skew among the output bits D0, D1, D2, etc. Ideally, the delays between the clock signals C0, C1, C2, etc. in the sampling clock path should be matched to the respectively corresponding delays in the data path through the binary ripple counter 12. In that case, if bit D0 can be sampled correctly at PHV(0), then bit D1 can also be sampled correctly at PHV(1), etc. This ideal situation is shown in FIG. 2, wherein each of the sample clock signals C0, C1, C2, etc. becomes active to sample the corresponding output bit D0, D1, D2, etc. after a common delay interval has elapsed since the transition of the corresponding output bit.
However, the required resolution of the delay matching between the clock path and the data path increases with increases in the operating speed. The error tolerance associated with the sampling points for more significant bits is the same as the error tolerance associated with the least significant bit D0, but larger delay mismatches can be expected for the more significant bits due to the accumulation of delay mismatches at each additional count stage of the counter. Consequently, the sampler 11 of FIG. 1 may not function suitably as the frequency of Clock 2 increases.
It is therefore desirable to provide for accurately sampling a binary ripple counter even at high operating frequencies.